To regulate the power rails on an integrated circuit such as a system-on-a-chip (SoC), it is conventional to use a switch-mode power supply (SMPS) due to its desirable efficiency as compared to alternative techniques such as a linear dropout regulator (LDO). To control the power switch cycling in an SMPS, it is also conventional to use a pulse-width modulation mode (PWM) controller due to its low-power consumption and greatly reduced complexity as compared to digital control schemes. Although PWM controllers are power efficient as compared to digital control schemes, the resulting feedback control loop suffers from startup problems.
To provide a better appreciation of these startup problems, consider a conventional switch-mode power supply 100 as illustrated in FIG. 1. A power switch 105 is cycled on and off with a duty cycle (pulse width) determined by a comparator 110. An input current is driven through power storage element 115 responsive to the input voltage while power switch 105 is conducting to store energy within power storage element 115. Power switch 105 is thus configured to control a current within power storage element 115. When power switch 105 switches off, the stored energy in power storage element 115 drives a load (not illustrated) with an output voltage Vout. A voltage scaling circuit 125 scales the output voltage to produce a scaled regulator output voltage that is compared to a reference voltage at an error amplifier 120 to produce an error voltage (error amplifier voltage signal). A digital-to-analog (DAC) converter 130 produces the reference voltage responsive to a band gap voltage (which may also be designated as a band gap reference or a band gap reference voltage) and a digital control signal.
The pulse-width modulation involves a ramp voltage generated by a ramp generator 135 at a ramp output signal node. The ramp voltage generation may be responsive to a clock signal such as a system clock signal. Comparator 110 compares the ramp voltage to the error voltage. As the scaled regulator output voltage changes in response to changes in the output voltage, an error voltage intersection with the ramp voltage changes accordingly. Comparator 110 will thus adjust the duty cycle of the cycling of power switch 105 so that the output voltage is regulated at the desired level. This desired amplitude for the output voltage is determined by the digital control signal (digital control word) controlling the reference voltage level at DAC 130.
Although such regulation of the output voltage in a switch-mode power supply is routine, note that the output voltage of error amplifier 120 will either be the power supply voltage VDD or ground upon startup as shown in FIG. 2A (a DC value for the ramp voltage as shown in FIG. 2A is discussed further herein). But to produce a pulsing of power switch 105, the error voltage (Verror, which may also be denoted as an error signal) must intersect with the ramp voltage (Vramp) as shown in FIG. 2B. In other words, the error voltage must have a value that lies between the maximum and minimum values of the ramp voltage. Since there is no such intersection in FIG. 2A, switch-mode power supply 100 would never go into regulation at startup with no further modifications. To address this startup issue, it is thus conventional to force power switch 105 to cycle upon startup in an open loop fashion (no feedback control through error amplifier 120 and comparator 110) and to then gradually increase the duty cycle of the power switch cycling so that the resulting error voltage has a value that lies between the maximum and minimum values for the ramp voltage. The loop is then closed so that the output voltage may be regulated in a conventional fashion. But this opening and closing of the control loop at startup of switch-mode power supply 100 results in delay and requires complicated circuitry to ensure a smooth transition into closed-loop operation.
Accordingly, there is a need in the art for pulse-width-modulated switch-mode power supplies having improved startup performance.